The present invention relates to a semiconductor device and, more particularly, to a technology effective if applied to the package of a large-scale integrated circuit of high integration.
In the prior art, the semiconductor chip is sealed up with a molding resin so that it may be protected. Several methods are used to mount leads in position on the semiconductor chip before the sealing.
For example, a lead frame having tabs at its center is used and mounted before the semiconductor chip is sealed. In this prior art, there is known a method of connecting electrode pads around the semiconductor chip with the corresponding inner leads through bonding wires.
The common problem among the semiconductor packages of the prior art is that the metal lead frame is cracked along the mold parting lines providing the exits or the lead lines
Another problem is that the passages or moisture or contaminants in the atmosphere to steal along the metal lead wires from the outside into the semiconductor chip are relatively short.
Moreover, the surface mounting type package is seriously troubled by the so-called “reflow cracking” problem that the moisture contained in the package is expanded by the heat of the solder reflow to crack the package.
Still another problem is that the bonding wires necessary for connecting the inner leads with the electrode pads of the semiconductor chip cannot be intersected partly because they are relatively long and partly because they are alternately assigned to input/output terminals.
In order to solve the above-specified problems, therefore, there has been proposed in Japanese Patent Laid-Open No. 241959/1986 (corresponding to E.P. Publication No. 0198194) a semiconductor device in which a plurality of inner leads are adhered to the circuit forming surface of a semiconductor chip through the semiconductor chip and insulating films by an adhesive, in which the inner leads and the semiconductor chip are electrically connected through bonding wires and in which common inner leads (or bus bar inner leads) are disposed in the vicinity of the longitudinal center line or the circuit forming surface of the semiconductor chip.
Also disclosed in Japanese Patent Laid-Open No. 167454/1985 or 218139/1986 (corresponding to U.S. Ser. No. 845.332) is the package structure of the so-called “tabless lead frame type”, in which the tabs (i.e., the die pads) mounting the chip are eliminated to mount the chip on the insulating films is adhered to the leads (i.e., Chip On Lead) and in which the bonding pads of the chip and the leading ends of the leads are connected through wires.
Also proposed in Japanese Patent Laid-Open No. 92556/1984 or 236130/1986 is the package structure in which the leads are adhered to the upper surface of the chip (i.e., Lead On Chip) by an adhesive and in which the bonding pads of the chip and the leading end portions of the leads are connected through wires.
According to the above-specified package structure arranged with the leads on the upper or lower surface of the chip, the heat and moisture resistances of the package can be improved because the leads in the package can be elongated. Thanks to the elimination of the tabs, moreover, the contact between the resin and the leads is improved to improve the reflow cracking resistance. As a result, even the large-sized chip can be packed in the package of the existing size. Moreover, this package structure is advantageous in reducing the wiring delay because it can shorten the bonding wires.